This invention relates generally to electronic circuits and in particular to an electronic circuit configured as a current mirror, and is more particularly directed toward a current mirror having improved power supply rejection.
A current mirror is a current-controlled current source that ideally provides an output current that is constant for a given input current. Current mirror circuits are particularly useful in integrated circuit implementations of operational amplifiers, to establish the DC operating point (or bias condition) for the circuit. Using current mirrors, the output of a current source can be replicated where needed throughout a given circuit.
FIG. 1 depicts a simple current mirror, generally depicted by the numeral 100. Input current for the current mirror 100 is provided by a current source Iin 101, which has an output impedance represented by parallel resistor Ri 102. The connection 105 between the gate 103 and drain 104 of PMOS transistor MP1106 establishes the required gate-source voltage, Vgs, to carry the input current in transistor MP1106. MP2 replicates the input current 101 to the output Iout 108, since MP1 and MP2 have the same gate-source voltage Vgs. In an integrated circuit (IC) implementation, the ratio of Iout to Iin can be set by the ratio of the areas of MP2 to MP1.
If a disturbance voltage is added to the supply voltage VDD 109, an unwanted current will flow in the output Iout 108. Power supply rejection is the ability of the circuit 100 to minimize the unwanted current in the output Iout 108 in the presence of a disturbance on VDD 109.
A number of techniques have been proposed in an effort to improve the power supply rejection ratio (PSRR) of a current mirror. In U.S. Pat. No. 4,471,292, Schenck et al. propose operating the mirror transistors in their saturation region at an operating point that is close to the boundary between linearity and saturation. The point where Schenck et al. bias the transistors is optimized so that the current mirror occupies the minimum amount of headroom. This is at the expense of lower output impedance and PSRR. FIG. 2 of Schenck et al. shows that the output impedance degrades rapidly if VDS is slightly reduced. Random mismatches in device sizes may lead the circuit to operate in this undesired region. Essentially, Schenck et al. are biasing the circuit for minimum headroom at the expense of lower output impedance and PSRR and the risk of these parameters being degraded further. In addition, the technique described does not correct for unwanted current flowing in the output impedance of the input current source.
Tomasini et al., in U.S. Pat. No. 5,485,074, increase PSRR by cascoding the output transistor of the current mirror. However, it is known that cascoding results in higher operating voltage requirements for the current mirror, and may limit the range of circuits with which the current mirror can be employed without interposing level translation circuitry. Operating voltage margin is often expressed in terms of xe2x80x9cheadroom,xe2x80x9d which is the difference between the supply voltage and the required operating voltage.
Lambert, in U.S. Pat. No. 5,512,816, proposes to improve power supply rejection ratio by generating an error current that tracks power supply variations, then replicating the error current into a summing circuit that cancels out its effect. This method displays sensitivity to mismatch errors. Ierr is a small current, and it is sensitive to errors in current mirror 208 (FIG. 2 of Lambert) that subtracts it from the output. Mismatch error is caused by random area mismatches between two transistors that ideally should be the same size. Lambert does manage to correct for unwanted current that flows in the output impedance of Q203 due to VDD variations. In the circuit of FIG. 2, the input current can be a current source as shown, or a current sink connected to point 214. Another disadvantage of this circuit is that a correction current has to be subtracted from each replica of the input.
This disadvantage in particular is addressed in a modification of this technique set forth in U.S. Pat. No. 5,625,281, an op-amp loop to track the reference current in order to eliminate the need for error-subtraction at every current mirror output. However, this modified technique does not correct for unwanted current that flows in the output impedance of the input current source. This is because the circuit configuration requires that the input be a current source. The output impedance of the input current source is connected between VDD and a ground-referenced node, and hence will have an unwanted current flowing through it. This current is replicated to the output.
Because of the above-described shortcomings of prior art techniques, a need arises for a current mirror having improved power supply rejection that is relatively simple and economical in implementation, offers reduced sensitivity to mismatch errors, and minimizes supply voltage concerns related to headroom requirements.
These needs and others are satisfied by the present invention. In accordance with one aspect of the invention, a circuit comprises a current source providing an input current, first and second transistors having common control terminals and forming a current mirror connected between first and second power supply potentials, with the first transistor having an input coupled to the current source, the current mirror generating a mirror current at an output of the second transistor, and an amplifier connected in a negative feedback loop around the first transistor, wherein the amplifier input is referenced to the first power supply potential, and the amplifier output is referenced to the second power supply potential. The first and second transistors may comprise MOS transistors, with the common control terminals of the first and second transistors comprising common source terminals and common gate terminals.
In one form of the invention, the input current source is connected in series with the first transistor drain terminal, defining an amplifier input node therebetween. The amplifier output is then coupled to the common gate terminals of the first and second transistors. The first supply potential may be ground potential, while the second supply potential may be a positive power supply voltage coupled to the common source terminals of the first and second transistors.
In another form of the invention, the amplifier comprises an input stage including third and fourth transistors configured as a parallel transistor pair connected in series with a fifth transistor configured as a current source, and an output stage comprising a sixth transistor coupled to the input stage and in series with a diode-connected output transistor. The third and fourth transistors may be MOS transistors. The amplifier input signal may be applied to the gate terminal of the third transistor.
In still another form of the invention, the third and fourth transistors have common source terminals each coupled to the first power supply potential, and common drain terminals each coupled to the fifth transistor configured as a current source. A bias potential may be applied to a gate terminal of the fifth transistor to establish fifth transistor operating current. The bias potential is derived from the second power supply potential such that variations in the second power supply potential appear in the bias potential.
In still a further form of the invention, a gate terminal of the fourth transistor is coupled to the common drain terminals of the third and fourth transistors, the gate terminal defining both an output of the first amplifier stage and an input of the second amplifier stage. The sixth transistor further includes a source terminal coupled to the first power supply potential and a drain terminal coupled to common drain and gate terminals of the seventh diode-connected transistor. The seventh diode-connected transistor includes a source terminal coupled to the second power supply potential, wherein the common drain and gate terminals are coupled to the common gate terminals shared by the first and second transistors of the current mirror.
In accordance with another aspect of the invention, the amplifier comprises a single stage differential amplifier including third and fourth transistors configured as a differential transistor pair and sharing common source terminals, a current source interposed between the common source terminals and the first power supply potential, a fifth diode-connected transistor coupled between a drain terminal of the third transistor and the second power supply potential, a sixth diode-connected transistor coupled between a drain terminal of the fourth transistor and the second power supply potential, the sixth transistor having gate and drain electrodes connected together and coupled to the common gate terminals of the first and second transistors.
In accordance with a further aspect of the invention, a method is provided for improving power supply rejection ratio of a current mirror including first and second transistors having common control terminals and forming a current mirror connected between first and second power supply potentials, with the first transistor having an input coupled to an input current source, and the current mirror generating a mirror current at an output of the second transistor. The method comprises the steps of providing an amplifier in a negative feedback loop around the first transistor, configuring the amplifier such that the amplifier input is referenced to the first power supply potential, and configuring the amplifier such that the amplifier output is referenced to the second power supply potential. The negative feedback establishes a control voltage at one of the common control terminals to maintain substantial equality between the input current and the mirror current.
In accordance with yet a further aspect of the invention, a circuit comprises a current source providing an input current, first and second transconductors having common control terminals and forming a current mirror connected between first and second power supply potentials, with the first transconductor having an input coupled to the current source, the current mirror generating a mirror current at an output of the second transconductor, and an amplifier connected in a negative feedback loop around the first transconductor, wherein the amplifier input is referenced to the first power supply potential, and the amplifier output is referenced to the second power supply potential. The transconductors may comprise single transistors or cascoded transistors.
Further objects, features, and advantages of the present invention will become apparent from the following description and drawings.